1. Field of the Invention
The present invention relates to a comparator circuit, and more particularly, to a comparator circuit implemented in a memory chip.
2. Description of the Related Art
In general, a binary comparator circuit is used for receiving two binary numbers or streams (also referred to as “data”) and determining which is larger. The simplest form of a binary comparator circuit employs a method of receiving two binary numbers or streams to be compared, comparing the received two binary numbers or streams sequentially from MSB (Most Significant Bit) to LSB (Least Significant Bit), and determining whether one of the two binary numbers or streams is larger than the other based on the result of the comparison.
For example, if a single bit output of a conventional binary comparator circuit is 1, this means that one of two binary data is larger than the other. If a single output of the conventional binary comparator circuit is 0, this means that one of two binary data is not larger than the other. Such a conventional binary comparator circuit has a problem where the comparison speed of the binary comparator circuit decreases in proportion to the number of bits of input data.
A comparator circuit disclosed in U.S. Pat. No. 5,592,142 is directed to a method for receiving two data, calculating all cases simultaneously in which one of the received data may be determined to be larger than the other, and comparing the data to determine whether one of the cases is true. This conventional comparator circuit uses a gate as a fundamental unit and a critical path of the comparator circuit includes three gates. This comparator circuit requires numerous gates to compare two data. As a result, this conventional comparator circuit requires a large layout area and consumes large amount of power.